The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a trench isolation structure.
FIG. 1 generally shows a cross sectional view of a conventional semiconductor device having trench isolation. This conventional semiconductor device has a p-type substrate 10, trench isolations 11, and field effect transistors (FETs) 12 and 13. The trench isolation 11 consists of an oxide layer 11a formed within a trench 11b. The FET 12 has an n.sup.+ -type source (diffusion) region 12S, a p-type gate region 12G and an n.sup.+ -type drain (diffusion) region 12D. Similarly, the FET 13 has an n.sup.+ -type source (diffusion) region 13S, a p-type gate region 13G and an n.sup.+ -type drain (diffusion) region 13D.
FIG. 2 generally shows a plan view of the semiconductor device shown in FIG. 1. In FIG. 2, the same designations are used as in FIG. 1.
According to this conventional semiconductor device, an interface state is formed at an interface between the substrate 10 and the oxide layer 11a within the trench 11b. Hence, a depletion layer is formed at the interface. In this case, since the drain region 12D of the FET 12 and the source region 13S of the adjacent FET 13 are located on respective sides of the trench isolation 11, carriers from one of the regions 12D and 13S leak to the other of the regions 12D and 13S through the depletion layer, thereby causing an unwanted vertical direction leak current Lv to flow between the adjacent FETs 12 and 13. This vertical direction leak current Lv flows between two mutually adjacent elements of the semiconductor device.
On the other hand, the depletion layer is also formed at the side walls of the trench isolation 11 within the same FET 12, for example. Even when no gate voltage is applied to the gate region 12G, there is a problem in that a lateral direction leak current L1 flows between the source and drain regions 12S and 12D of the FET 12. This lateral direction leak current L1 flows within the same element of the semiconductor device.
FIG. 3 is a schematic view of the conventional semiconductor device shown in FIGS. 1 and 2 showing the vertical and lateral leak currents Lv and Ll. In FIG. 3, the same designations are used as in FIGS. 1 and 2.
In order to prevent the formation of the depletion layer at the interface between the substrate 10 and the oxide layer 11a within the trench 11b, it is known to implant boron (B) impurities at the interface with an impurity concentration greater than that of the substrate 10, as shown in FIG. 4. In FIG. 4, those parts which are the same as those corresponding parts in FIG. 3 are designated by the same reference numerals, and a description thereof will be omitted. In this case, a boron (B) layer 15 is formed at the interface and it is possible to prevent the formation of the depletion layer so as to prevent the vertical and lateral leak currents Lv and Ll from being generated.
However, during a thermal process which is carried out after the B impurities are implanted, the B impurities are widely diffused within the substrate 10 due to the thermal process and the so-called narrow channel effect occurs. A narrow channel is indicated by NC in FIG. 4. For this reason, the semiconductor device shown in FIG. 4 suffers a problem in that the current driving capability of the FET 12 is deteriorated by the narrow channel NC.